System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-109
ID021414 Non-Confidential
Table 4-100 shows the L2ECTLR_EL1 bit assignments.
To access the L2ECTLR_EL1:
MRS Rt, S3_1_C11_C0_3; Read L2ECTLR_EL1 into Rt
MSR S3_1_C11_C0_3, Rt; Write Rt to L2ECTLR_EL1
4.3.66 L2 Auxiliary Control Register
The L2ACTLR_EL1 characteristics are:
Purpose Provides configuration and control options for the L2 memory system.
Usage constraints This register is accessible as follows:
The L2ACTLR_EL1:
• This register can be written only when the L2 memory system is
idle. ARM recommends that you write to this register after a
powerup reset before the MMU is enabled and before any ACE, CHI
or ACP traffic has begun.
Table 4-100 L2ECTLR_EL1 bit assignments
Bits Name Function
[31] - Reserved,
RES0.
[30] L2 internal asynchronous error L2 internal asynchronous error caused by L2 RAM double-bit ECC error. The possible
values are:
0
No pending asynchronous error. This is the reset value.
1
An asynchronous error has occurred.
A write of
0
clears this bit and drives nINTERRIRQ HIGH. A write of
1
is ignored.
[29] AXI or CHI asynchronous error AXI or CHI asynchronous error indication. The possible values are:
0
No pending asynchronous error.
1
An asynchronous error has occurred.
A write of
0
clears this bit and drives nEXTERRIRQ HIGH. A write of
1
is ignored.
[28:3] - Reserved,
RES0.
[2:0] L2 dynamic retention control L2 dynamic retention control. The possible values are:
0b000
L2 dynamic retention disabled. This is the reset value.
0b001
2 Generic Timer ticks required before retention entry.
0b010
8 Generic Timer ticks required before retention entry.
0b011
32 Generic Timer ticks required before retention entry.
0b100
64 Generic Timer ticks required before retention entry.
0b101
128 Generic Timer ticks required before retention entry.
0b110
256 Generic Timer ticks required before retention entry.
0b111
512 Generic Timer ticks required before retention entry.
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RWRWRWRW RW
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