System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-108
ID021414 Non-Confidential
Usage constraints This register is accessible as follows:
The L2ECTLR_EL1 can be written dynamically.
Configurations L2ECTLR_EL1 is architecturally mapped to the AArch32 L2ECTLR
register. See L2 Extended Control Register on page 4-253
There is one copy of this register that is used in both Secure and
Non-secure states.
There is one L2ECTLR_EL1 for the Cortex-A53 processor.
Attributes L2ECTLR_EL1 is a 32-bit register.
Figure 4-59 shows the L2ECTLR_EL1 bit assignments.
Figure 4-59 L2ECTLR_EL1 bit assignments
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RWRWRWRW RW
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