System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-116
ID021414 Non-Confidential
Table 4-104 shows the PAR_EL1 bit assignments when the Virtual Address to Physical Address
conversion is aborted.
To access the PAR_EL1:
MRS <Xt>, PAR_EL1 ; Read EL1 Physical Address Register
MSR PAR_EL1, <Xt> ; Write EL1 Physical Address Register
4.3.69 Memory Attribute Indirection Register, EL1
The MAIR_EL1 characteristics are:
Purpose Provides the memory attribute encodings corresponding to the possible
AttrIndx values in a Long-descriptor format translation table entry for
stage 1 translations at EL1.
Usage constraints This register is accessible as follows:
MAIR_EL1 is permitted to be cached in a TLB.
Configurations MAIR_EL1[31:0] is architecturally mapped to AArch32 register:
• PRRR (NS) when TTBCR.EAE is 0. See Primary Region Remap
Register on page 4-256.
• MAIR0 (NS) when TTBCR.EAE is 1. See Memory Attribute
Indirection Registers 0 and 1 on page 4-259.
Table 4-104 PAR_EL1 fail bit assignments
Bits Name Function
[63:12] - Reserved,
RES0.
[11] - Reserved,
RES1.
[10] - Reserved,
RES0.
[9] S Stage of fault. Indicates the state where the translation aborted. The possible values are:
0
Translation aborted because of a fault in stage 1 translation.
1
Translation aborted because of a fault in stage 2 translation.
[8] PTW Indicates a stage 2 fault during a stage 1 table walk. The possible values are:
0
No stage 2 fault during a stage 1 table walk.
1
Translation aborted because of a stage 2 fault during a stage 1 table walk.
[7] - Reserved,
RES0.
[6:1] FST
Fault status code, as shown in the Data Abort ESR encoding. See the ARM
®
Architecture Reference Manual
ARMv8, for ARMv8-A architecture profile for more information.
[0] F Pass/Fail bit. Indicates whether the conversion completed successfully. This value is:
1
Virtual Address to Physical Address conversion aborted.
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RWRWRWRW RW
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