System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-117
ID021414 Non-Confidential
MAIR_EL1[63:32] is architecturally mapped to AArch32 register:
• NMRR (NS) when TTBCR.EAE is 0. See Normal Memory Remap
Register on page 4-262.
• MAIR1(NS) when TTBCR.EAE is 1. See Memory Attribute
Indirection Registers 0 and 1 on page 4-259.
Attributes MAIR_EL1 is a 64-bit register.
Figure 4-64 shows the MAIR_EL1 bit assignments.
Figure 4-64 MAIR_EL1 bit assignments
Attr<n> is the memory attribute encoding for an AttrIndx[2:0] entry in a Long descriptor format
translation table entry, where AttrIndx[2:0] gives the value of <n> in Attr<n>.
Table 4-105 shows the encoding of bits [7:4] of the Attr<n> field.
Table 4-106 shows the encoding of bits [0:3] of the Attr<n> field.
Table 4-105 Attr<n>[7:4] bit assignments
Bits Meaning
0b0000
Device memory. See Table 4-106 for the type of Device memory.
0b00RW
, RW not
00
Normal Memory, Outer Write-through transient.
a
a. The transient hint is ignored.
0b0100
Normal Memory, Outer Non-Cacheable.
0b01RW
, RW not
00
Normal Memory, Outer Write-back transient.
a
0b10RW
Normal Memory, Outer Write-through non-transient.
0b11RW
Normal Memory, Outer Write-back non-transient.
Table 4-106 Attr<n>[3:0] bit assignments
Bits Meaning when Attr<n>[7:4] is 0000 Meaning when Attr<n>[7:4] is not 0000
0b0000
Device-nGnRnE memory UNPREDICTABLE
0b00RW
, RW not
00
UNPREDICTABLE Normal Memory, Inner Write-through transient
0b0100
Device-nGnRE memory Normal memory, Inner Non-Cacheable
0b01RW
, RW not
00
UNPREDICTABLE Normal Memory, Inner Write-back transient
0b1000
Device-nGRE memory Normal Memory, Inner Write-through
non-transient (RW=00)
0b10RW
, RW not
00
UNPREDICTABLE Normal Memory, Inner Write-through non-transient
0b1100
Device-GRE memory Normal Memory, Inner Write-back non-transient (RW=00)
0b11RW
, RW not
00
UNPREDICTABLE Normal Memory, Inner Write-back non-transient
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