System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-118
ID021414 Non-Confidential
Table 4-107 shows the encoding of the R and W bits that are used, in some Attr<n> encodings
in Table 4-105 on page 4-117 and Table 4-106 on page 4-117, to define the read-allocate and
write-allocate policies:
To access the MAIR_EL1:
MRS <Xt>, MAIR_EL1 ; Read EL1 Memory Attribute Indirection Register
MSR MAIR_EL1, <Xt> ; Write EL1 Memory Attribute Indirection Register
4.3.70 Memory Attribute Indirection Register, EL2
The MAIR_EL2 characteristics are:
Purpose Provides the memory attribute encodings corresponding to the possible
AttrIndx values in a Long-descriptor format translation table entry for
stage 1 translations at EL2.
Usage constraints This register is accessible as follows:
MAIR_EL2 is permitted to be cached in a TLB.
Configurations MAIR_EL2[31:0] is architecturally mapped to AArch32 register
HMAIR0.
MAIR_EL2[63:32] is architecturally mapped to AArch32 register
HMAIR1.
Attributes MAIR_EL2 is a 64-bit register.
The MAIR_EL2 bit assignments follow the same pattern as described in Figure 4-64 on
page 4-117.
The description of the MAIR_EL2 bit assignments are the same as described in Table 4-105 on
page 4-117 and Table 4-108 on page 4-120.
To access the MAIR_EL2:
MRS <Xt>, MAIR_EL2 ; Read EL2 Memory Attribute Indirection Register
MSR MAIR_EL2, <Xt> ; Write EL2 Memory Attribute Indirection Register
4.3.71 Memory Attribute Indirection Register, EL3
The MAIR_EL3 characteristics are:
Purpose Provides the memory attribute encodings corresponding to the possible
AttrIndx values in a Long-descriptor format translation table entry for
stage 1 translations at EL3.
Table 4-107 Encoding of R and W bits in some Attrm fields
R or W Meaning
0 Do not allocate
1 Allocate
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-- -RWRW RW
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