System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-119
ID021414 Non-Confidential
Usage constraints This register is accessible as follows:
MAIR_EL2 is permitted to be cached in a TLB.
Configurations MAIR_EL3[31:0] is mapped to AArch32 register PRRR (S) when
TTBCR.EAE is 0. See Primary Region Remap Register on page 4-256.
MAIR_EL3[63:32] is mapped to AArch32 register NMRR (S) when
TTBCR.EAE is 0. See Normal Memory Remap Register on page 4-262.
Attributes MAIR_EL3 is a 64-bit register.
The MAIR_EL3 bit assignments follow the same pattern as described in Figure 4-64 on
page 4-117.
The description of the MAIR_EL3 bit assignments are the same as described in Table 4-105 on
page 4-117 and Table 4-108 on page 4-120.
To access the MAIR_EL3:
MRS <Xt>, MAIR_EL3 ; Read EL3 Memory Attribute Indirection Register
MSR MAIR_EL3, <Xt> ; Write EL3 Memory Attribute Indirection Register
4.3.72 Vector Base Address Register, EL1
The VBAR_EL1 characteristics are:
Purpose Holds the exception base address for any exception that is taken to EL1.
Usage constraints This register is accessible as follows:
Configurations The VBAR_EL1[31:0] is architecturally mapped to the Non-secure
AArch32 VBAR register. See Vector Base Address Register on
page 4-263.
Attributes VBAR_EL1 is a 64-bit register.
Figure 4-65 shows the VBAR_EL1 bit assignments.
Figure 4-65 VBAR_EL1 bit assignments
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-- --RW RW
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RWRWRWRW RW
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