System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-120
ID021414 Non-Confidential
Table 4-108 shows the VBAR_EL1 bit assignments.
To access the VBAR_EL1:
MRS <Xt>, VBAR_EL1 ; Read VBAR_EL1 into Xt
MSR VBAR_EL1, <Xt> ; Write Xt to VBAR_EL1
4.3.73 Vector Base Address Register, EL2
The VBAR_EL2 characteristics are:
Purpose Holds the exception base address for any exception that is taken to EL2.
Usage constraints This register is accessible as follows:
Configurations The VBAR_EL2[31:0] is architecturally mapped to the AArch32 HVBAR
register. See Hyp Vector Base Address Register on page 4-266.
Attributes VBAR_EL2 is a 64-bit register.
Figure 4-66 shows the VBAR_EL2 bit assignments.
Figure 4-66 VBAR_EL2 bit assignments
Table 4-109 shows the VBAR_EL2 bit assignments.
To access the VBAR_EL2:
MRS <Xt>, VBAR_EL2 ; Read VBAR_EL2 into Xt
MSR VBAR_EL2, <Xt> ; Write Xt to VBAR_EL2
Table 4-108 VBAR_EL1 bit assignments
Bits Name Function
[63:11] Vector base address Base address of the exception vectors for exceptions taken in this exception level.
[10:0] - Reserved, RES0.
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-- -RWRW RW
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