ARM Cortex-A53 MPCore - Page 182

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-121
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Register access is encoded as follows:
4.3.74 Vector Base Address Register, EL3
The VBAR_EL3 characteristics are:
Purpose Holds the exception base address for any exception that is taken to EL3.
Usage constraints This register is accessible as follows:
Configurations The VBAR_EL3[31:0] is mapped to the Secure AArch32 VBAR register.
See Vector Base Address Register on page 4-263.
Attributes VBAR_EL3 is a 64-bit register.
Figure 4-67 shows the VBAR_EL3 bit assignments.
Figure 4-67 VBAR_EL3 bit assignments
Table 4-111 shows the VBAR_EL3 bit assignments.
To access the VBAR_EL3:
MRS <Xt>, VBAR_EL3 ; Read EL3 Vector Base Address Register
MSR VBAR_EL3, <Xt> ; Write EL3 Vector Base Address Register
4.3.75 Reset Vector Base Address Register, EL3
The RVBAR_EL3 characteristics are:
Purpose Contains the address that execution starts from after reset when executing
in the AArch64 state.
RVBAR_EL3 is part of the Reset management registers functional group.
Table 4-110 VBAR_EL2 access encoding
op0 op1 CRn CRm op2
11 100 1100 0000 000
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-- --RW RW
63 0
RES
0
11 10
Vector base address
Table 4-111 VBAR_EL3 bit assignments
Bits Name Function
[63:11] Vector base address Base address of the exception vectors for exceptions taken in this exception level.
[10:0] - Reserved,
RES0.