ARM Cortex-A53 MPCore - Page 183

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-122
ID021414 Non-Confidential
Usage constraints This register is accessible as follows:
Configurations There is no configuration information.
Attributes RVBAR_EL3 is a 64-bit register.
Figure 4-68 shows the RVBAR_EL3 bit assignments.
Figure 4-68 RVBAR_EL3 bit assignments
Table 4-112 shows the RVBAR_EL3 bit assignments.
To access the RVBAR_EL3:
MRS <Xt>, RVBAR_EL3 ; Read RVBAR_EL3 into Xt
4.3.76 Reset Management Register
The RMR_EL3 characteristics are:
Purpose Controls the execution state that the processor boots into and allows
request of a warm reset.
Usage constraints This register is accessible as follows:
Configurations The RMR_EL3 is architecturally mapped to the AArch32 RMR register.
Attributes RMR_EL3 is a 32-bit register.
Figure 4-69 on page 4-123 shows the RMR_EL3 bit assignments.
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-- --RO RO
0
Reset Vector Base Address
63
Table 4-112 RVBAR_EL3 bit assignments
Bits Name Function
[63:0] RVBA Reset Vector Base Address. The address that execution starts from after reset when executing in 64-bit state.
Bits[1:0] of this register are
0b00 , as this address must be aligned, and bits [63:40] are 0x000000 because the address
must be within the physical address size supported by the processor.
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-- --RW RW