System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-127
ID021414 Non-Confidential
To access the CPUACTLR_EL1:
MRS <Xt>, S3_1_C15_C2_0 ; Read EL1 CPU Auxiliary Control Register
MSR S3_1_C15_C2_0, <Xt> ; Write EL1 CPU Auxiliary Control Register
[22] STBPFDIS Disable prefetch streams initiated from STB accesses:
0
Enable Prefetch streams initiated from STB accesses. This is the reset value.
1
Disable Prefetch streams initiated from STB accesses.
[21] IFUTHDIS IFU fetch throttle disabled. The possible values are:
0
Fetch throttle enabled. This is the reset value.
1
Fetch throttle disabled. This setting increases power consumption.
[20:19] NPFSTRM Number of independent data prefetch streams. The possible values are:
0b00
1 stream.
0b01
2 streams. This is the reset value.
0b10
3 streams.
0b11
4 streams.
[18] DSTDIS Enable device split throttle. The possible values are:
0
Device split throttle disabled.
1
Device split throttle enabled. This is the reset value.
[17] STRIDE Configure the sequence length that triggers data prefetch streams. The possible values are:
0
2 linefills to consecutive cache lines triggers prefetch. This is the reset value.
1
3 linefills to consecutive cache lines triggers prefetch.
In both configurations, Three linefills with a fixed stride pattern are required to trigger prefetch, if the stride
spans more than one cache line.
[16] - Reserved, RES0.
[15:13] L1PCTL L1 Data prefetch control. The value of the this field determines the maximum number of outstanding data
prefetches allowed in the L1 memory system, excluding those generated by software load or PLD
instructions. The possible values are:
0b000
Prefetch disabled.
0b001
1 outstanding prefetch allowed.
0b010
2 outstanding prefetches allowed.
0b011
3 outstanding prefetches allowed.
0b100
4 outstanding prefetches allowed.
0b101
5 outstanding prefetches allowed. This is the reset value.
0b110
6 outstanding prefetches allowed.
0b111
8 outstanding prefetches allowed.
[12:11] - Reserved,
RES0.
[10] DODMBS Disable optimized Data Memory Barrier behavior. The possible values are:
0
Enable optimized Data Memory Barrier behavior. This is the reset value.
1
Disable optimized Data Memory Barrier behavior.
[9:0] - Reserved,
RES0.
Table 4-116 CPUACTLR_EL1 bit assignments (continued)
Bits Name Function
To Next Page
Loading...
