System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-128
ID021414 Non-Confidential
4.3.79 CPU Extended Control Register, EL1
The CPUECTLR_EL1 characteristics are:
Purpose Provides additional
IMPLEMENTATION DEFINED configuration and control
options for the processor.
Usage constraints This register is accessible as follows:
The CPUECTLR_EL1 can be written dynamically.
The CPUECTLR_EL1 is write accessible in EL1 if
ACTLR_EL3.CPUECTLR is 1 and ACTLR_EL2.CPUECTLR is 1, or
ACTLR_EL3.CPUECTLR is 1 and SCR.NS is 0.
The CPUECTLR_EL1 is write accessible in EL2 if
ACTLR_EL3.CPUECTLR is 1.
Configurations The CPUECTLR_EL1 is:
• Architecturally mapped to the AArch32 CPUECTLR register. See
CPU Extended Control Register on page 4-271.
Attributes CPUECTLR_EL1 is a 64-bit register.
Figure 4-72 shows the CPUECTLR_EL1 bit assignments.
Figure 4-72 CPUECTLR_EL1 bit assignments
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
-RWRWRWRW RW
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