ARM Cortex-A53 MPCore - Page 202

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-141
ID021414 Non-Confidential
4.4.9 c9 registers
Table 4-130 shows the 32-bit wide system registers you can access when the processor is in
AArch32 state and the value of CRn is c9. See the ARM
®
Architecture Reference Manual
ARMv8, for ARMv8-A architecture profile for more information.
Table 4-130 c9 register summary
CRn Op1 CRm Op2 Name Reset Description
c90c120PMCR
0x41033000 Performance Monitors Control Register on page 12-16
1 PMNCNTENSET UNK Performance Monitors Count Enable Set Register
2 PMNCNTENCLR UNK Performance Monitors Count Enable Clear Register
3 PMOVSR UNK Performance Monitor Overflow Flag Status Clear Register
4 PMSWINC UNK Performance Monitors Software Increment Register
5 PMSELR UNK Performance Monitors Event Counter Selection Register
6PMCEID0
0x67FFBFFF
a
Performance Monitors Common Event Identification Register
0 on page 12-18
7PMCEID1
0x00000000 Performance Monitors Common Event Identification Register
1 on page 12-21
c13 0 PMCCNTR UNK Performance Monitors Cycle Counter
1 PMXEVTYPER UNK Performance Monitors Selected Event Type and Filter
Register
2 PMXEVCNTR UNK Performance Monitors Selected Event Counter Register
c14 0 PMUSERENR
0x00000000 Performance Monitors User Enable Register
1 PMINTENSET UNK Performance Monitors Interrupt Enable Set Register
2 PMINTENCLR UNK Performance Monitors Interrupt Enable Clear Register
3 PMOVSSET UNK Performance Monitor Overflow Flag Status Set Register
1c02L2CTLR
-
b
L2 Control Register on page 4-251
3L2ECTLR
0x00000000 L2 Extended Control Register on page 4-253
a. The reset value is 0x663FBFFF if L2 cache is not implemented.
b. The reset value depends on the processor configuration.