System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-140
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4.4.6 c5 registers
Table 4-127 shows the 32-bit wide system registers you can access when the processor is in
AArch32 state and the value of CRn is c5.
4.4.7 c6 registers
Table 4-128 shows the 32-bit wide system registers you can access when the processor is in
AArch32 state and the value of CRn is c6.
4.4.8 c7 registers
Table 4-129 shows the 32-bit wide system registers you can access when the processor is in
AArch32 state and the value of CRn is c7. See the ARM
®
Architecture Reference Manual
ARMv8, for ARMv8-A architecture profile for more information.
Table 4-127 c5 register summary
CRn Op1 CRm Op2 Name Reset Description
c5 0 c0 0 DFSR UNK Data Fault Status Register on page 4-239
1 IFSR UNK Instruction Fault Status Register on page 4-243
c1 0 ADFSR
0x00000000
Auxiliary Data Fault Status Register on page 4-246
1AIFSR
0x00000000
Auxiliary Instruction Fault Status Register on page 4-246
c5 4 c1 0 HADFSR
0x00000000
Hyp Auxiliary Data Fault Status Syndrome Register on page 4-246
1 HAIFSR
0x00000000
Hyp Auxiliary Instruction Fault Status Syndrome Register on page 4-246
c2 0 HSR UNK Hyp Syndrome Register on page 4-246
Table 4-128 c6 register summary
CRn Op1 CRm Op2 Name Reset Description
c6 0 c0 0 DFAR UNK Data Fault Address Register on page 4-247
2 IFAR UNK Instruction Fault Address Register on page 4-248
4 c0 0 HDFAR UNK Hyp Data Fault Address Register on page 4-249
2 HIFAR UNK Hyp Instruction Fault Address Register on page 4-250
4 HPFAR UNK Hyp IPA Fault Address Register on page 4-250
Table 4-129 c7 register summary
CRn Op1 CRm Op2 Name Reset Description
c7 0 c4 0 PAR UNK Physical Address Register on page 4-251
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