System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-139
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4.4.3 c2 registers
Table 4-124 shows the 32-bit wide system registers you can access when the processor is in
AArch32 state and the value of CRn is c2.
4.4.4 c3 registers
Table 4-125 shows the 32-bit wide system registers you can access when the processor is in
AArch32 state and the value of CRn is c3.
4.4.5 c4 registers
Table 4-124 shows the 32-bit wide system registers you can access when the processor is in
AArch32 state and the value of CRn is c4.
Table 4-124 c2 register summary
CRn Op1 CRm Op2 Name Reset Description
c2 0 c0 0 TTBR0 UNK Translation Table Base Register 0 on page 4-224
1 TTBR1 UNK Translation Table Base Register 1 on page 4-226
2 TTBCR
0x00000000
a
Hyp Translation Control Register on page 4-232
4 c0 2 HTCR UNK Hyp Translation Control Register on page 4-232
c1 2 VTCR UNK Virtualization Translation Control Register on page 4-233
a. The reset value is
0x00000000
for the Secure copy of the register. The reset value for the EAE bit of the Non-secure copy of
the register is
0x0
. You must program the Non-secure copy of the register with the required initial value, as part of the
processor boot sequence.
Table 4-125 c3 register summary
CRn Op1 CRm Op2 Name Reset Description
c3 0 c0 0 DACR UNK Domain Access Control Register on page 4-235
Table 4-126 c3 register summary
CRn Op1 CRm Op2 Name Reset Description
c4 0 c6 0 ICC_PMR
0x00000000
Priority Mask Register
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