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ARM Cortex-A53 MPCore
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System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-168
ID021414 Non-Confidential
Register access is encoded as follows:
4.5.12 Memory Model Feature Register 2
The ID_MMFR2 characteristics are:
Purpose Provides information about the implemented memory model and memory
management support in AArch32.
Usage constraints This register is accessible as follows:
Must be interpreted with ID_MMFR0, ID_MMFR1, and ID_MMFR3.
See:
Memory Model Feature Register 0 on page 4-165.
Memory Model Feature Register 1 on page 4-166.
Memory Model Feature Register 3 on page 4-170
.
Configurations ID_MMFR2 is architecturally mapped to AArch64 register
ID_MMFR2_EL1.
There is one copy of this register that is used in both Secure and
Non-secure states.
Attributes ID_MMFR2 is a 32-bit register.
Figure 4-84 shows the ID_MMFR2 bit assignments.
Figure 4-84 ID_MMFR2 bit assignments
Table 4-163 ID_MMFR1 access encoding
coproc opc1 CRn CRm opc2
1111 000 0000 0001 101
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
--RORORORO RO
31 12 11 8 7 0
HWAccFlg
4328 27 24 23 20 19 16 15
WFIStall MemBarr UniTLB HvdTLB LL1HvdRng L1HvdBG L1HvdFG

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