ARM Cortex-A53 MPCore - Page 231

System Control
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4.5.13 Memory Model Feature Register 3
The ID_MMFR3 characteristics are:
Purpose Provides information about the memory model and memory management
support in AArch32.
Usage constraints This register is accessible as follows:
Must be interpreted with ID_MMFR0, ID_MMFR1, and ID_MMFR2.
See:
• Instruction Set Attribute Register 0 on page 4-172
• Memory Model Feature Register 1 on page 4-166
• Memory Model Feature Register 2 on page 4-168
Configurations ID_MMFR3 is architecturally mapped to AArch64 register
ID_MMFR3_EL1. See AArch32 Memory Model Feature Register 3 on
page 4-26.
There is one copy of this register that is used in both Secure and
Non-secure states.
Attributes ID_MMFR3 is a 32-bit register.
Figure 4-85 shows the ID_MMFR3 bit assignments.
Figure 4-85 ID_MMFR3 bit assignments
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
--RORORORO RO
31 12 11 8 7 04328 27 24 23 20 19 16 15
ReservedCohWalkCMemSzSupersec MaintBcst BPMaint CMaintSW CMaintVA