System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-171
ID021414 Non-Confidential
Table 4-166 shows the ID_MMFR3 bit assignments.
To access the ID_MMFR3:
MRC p15, 0, <Rt>, c0, c1, 7; Read ID_MMFR3 into Rt
Register access is encoded as follows:
Table 4-166 ID_MMFR3 bit assignments
Bits Name Function
[31:28] Supersec Supersections. Indicates support for supersections:
0x0
Supersections supported.
[27:24] CMemSz Cached Memory Size. Indicates the size of physical memory supported by the processor caches:
0x2
1TByte, corresponding to a 40-bit physical address range.
[23:20] CohWalk Coherent walk. Indicates whether translation table updates require a clean to the point of unification:
0x1
Updates to the translation tables do not require a clean to the point of unification to ensure
visibility by subsequent translation table walks.
[19:16] - Reserved,
RES0.
[15:12] MaintBcst Maintenance broadcast. Indicates whether cache, TLB and branch predictor operations are broadcast:
0x2
Cache, TLB and branch predictor operations affect structures according to shareability and
defined behavior of instructions.
[11:8] BPMaint Branch predictor maintenance. Indicates the supported branch predictor maintenance operations.
0x2
Supported branch predictor maintenance operations are:
• Invalidate all branch predictors.
• Invalidate branch predictors by MVA.
[7:4] CMaintSW Cache maintenance by set/way. Indicates the supported cache maintenance operations by set/way.
0x1
Supported hierarchical cache maintenance operations by set/way are:
• Invalidate data cache by set/way.
• Clean data cache by set/way.
• Clean and invalidate data cache by set/way.
[3:0] CMaintVA Cache maintenance by MVA. Indicates the supported cache maintenance operations by MVA.
0x1
Supported hierarchical cache maintenance operations by MVA are:
• Invalidate data cache by MVA.
a
• Clean data cache by MVA.
• Clean and invalidate data cache by MVA.
• Invalidate instruction cache by MVA.
• Invalidate all instruction cache entries.
a. Invalidate data cache by MVA operations are treated as clean and invalidate data cache by MVA operations on the executing core. If the
operation is broadcast to another core then it is broadcast as an invalidate data cache by MVA operation.
Table 4-167 ID_MMFR3 access encoding
coproc opc1 CRn CRm opc2
1111 000 0000 0001 111
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