ARM Cortex-A53 MPCore - Page 234

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-173
ID021414 Non-Confidential
Table 4-168 shows the ID_ISAR0 bit assignments.
To access the ID_ISAR0:
MRC p15, 0, <Rt>, c0, c2, 0 ; Read ID_ISAR0 into Rt
Register access is encoded as follows:
4.5.15 Instruction Set Attribute Register 1
The ID_ISAR1 characteristics are:
Purpose Provides information about the instruction sets implemented by the
processor in AArch32.
Usage constraints This register is accessible as follows:
Table 4-168 ID_ISAR0 bit assignments
Bits Name Function
[31:28] - Reserved,
RES0.
[27:24] Divide Indicates the implemented Divide instructions:
0x2 • SDIV and UDIV in the T32 instruction set.
•
SDIV and UDIV in the A32 instruction set.
[23:20] Debug Indicates the implemented Debug instructions:
0x1 BKPT .
[19:16] Coproc Indicates the implemented Coprocessor instructions:
0x0 None implemented, except for separately attributed by the architecture including CP15,
CP14, Advanced SIMD and Floating-point.
[15:12] CmpBranch Indicates the implemented combined Compare and Branch instructions in the T32 instruction set:
0x1 CBNZ and CBZ .
[11:8] Bitfield Indicates the implemented bit field instructions:
0x1 BFC , BFI , SBFX , and UBFX .
[7:4] BitCount Indicates the implemented Bit Counting instructions:
0x1 CLZ .
[3:0] Swap Indicates the implemented Swap instructions in the A32 instruction set:
0x0 None implemented.
Table 4-169 ID_ISAR0 access encoding
coproc opc1 CRn CRm opc2
1111 000 0000 0010 000
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
--RORORORO RO