System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-174
ID021414 Non-Confidential
Must be interpreted with ID_ISAR0, ID_ISAR2, ID_ISAR3, ID_ISAR4
and ID_ISAR5. See:
• Instruction Set Attribute Register 0 on page 4-172.
• Instruction Set Attribute Register 2 on page 4-175.
• Instruction Set Attribute Register 3 on page 4-178.
• Instruction Set Attribute Register 4 on page 4-179.
• Instruction Set Attribute Register 5 on page 4-181.
Configurations ID_ISAR1 is architecturally mapped to AArch64 register
ID_ISAR1_EL1. See AArch32 Instruction Set Attribute Register 1 on
page 4-29.
There is one copy of this register that is used in both Secure and
Non-secure states.
Attributes ID_ISAR1 is a 32-bit register.
Figure 4-87 shows the ID_ISAR1 bit assignments.
Figure 4-87 ID_ISAR1 bit assignments
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
Jazelle Interwork Immediate IfThen Extend Except_AR Except Endian
To Next Page
Loading...
