ARM Cortex-A53 MPCore - Page 242

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-181
ID021414 Non-Confidential
Table 4-176 shows the ID_ISAR4 bit assignments.
To access the ID_ISAR4:
MRC p15, 0, <Rt>, c0, c2, 4 ; Read ID_ISAR4 into Rt
Register access is encoded as follows:
4.5.19 Instruction Set Attribute Register 5
The ID_ISAR5 characteristics are:
Purpose Provides information about the instruction sets that the processor
implements.
Table 4-176 ID_ISAR4 bit assignments
Bits Name Function
[31:28] SWP_frac Indicates support for the memory system locking the bus for
SWP or SWPB instructions:
0x0 SWP and SWPB instructions not implemented.
[27:24] PSR_M Indicates the implemented M profile instructions to modify the PSRs:
0x0 None implemented.
[23:20] SynchPrim_frac This field is used with the ID_ISAR3.SynchPrim field to indicate the implemented Synchronization
Primitive instructions:
0x0 • The LDREX and STREX instructions.
• The
CLREX , LDREXB , LDREXH , STREXB , and STREXH instructions.
• The
LDREXD and STREXD instructions.
[19:16] Barrier Indicates the supported Barrier instructions in the A32 and T32 instruction sets:
0x1 The DMB , DSB , and ISB barrier instructions.
[15:12] SMC Indicates the implemented
SMC instructions:
0x1 The SMC instruction.
[11:8] Writeback Indicates the support for writeback addressing modes:
0x1 Processor supports all of the writeback addressing modes defined in ARMv8.
[7:4] WithShifts Indicates the support for instructions with shifts:
0x4 • Support for shifts of loads and stores over the range LSL 0-3.
• Support for other constant shift options, both on load/store and other instructions.
• Support for register-controlled shift options.
[3:0] Unpriv Indicates the implemented unprivileged instructions:
0x2 • The LDRBT , LDRT , STRBT , and STRT instructions.
• The
LDRHT , LDRSBT , LDRSHT , and STRHT instructions.
Table 4-177 ID_ISAR4 access encoding
coproc opc1 CRn CRm opc2
1111 000 0000 0010 100