System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-182
ID021414 Non-Confidential
Usage constraints This register is accessible as follows:
ID_ISAR5 must be interpreted with ID_ISAR0, ID_ISAR1, ID_ISAR2,
ID_ISAR3, and ID_ISAR4. See:
• Instruction Set Attribute Register 0 on page 4-172.
• Instruction Set Attribute Register 1 on page 4-173.
• Instruction Set Attribute Register 2 on page 4-175.
• Instruction Set Attribute Register 3 on page 4-178.
• Instruction Set Attribute Register 4 on page 4-179.
Configurations ID_ISAR5 is architecturally mapped to AArch64 register
ID_ISAR5_EL1. See AArch32 Instruction Set Attribute Register 5 on
page 4-36.
There is one copy of this register that is used in both Secure and
Non-secure states.
Attributes ID_ISAR5 is a 32-bit register.
Figure 4-91 shows the ID_ISAR5 bit assignments.
Figure 4-91 ID_ISAR5 bit assignments
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
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