ARM Cortex-A53 MPCore - Page 244

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-183
ID021414 Non-Confidential
Table 4-178 shows the ID_ISAR5 bit assignments.
To access the ID_ISAR5:
MRC p15,0,<Rt>,c0,c2,5 ; Read ID_ISAR5 into Rt
Register access is encoded as follows:
4.5.20 Cache Size ID Register
The CCSIDR characteristics are:
Purpose Provides information about the architecture of the caches.
Usage constraints This register is accessible as follows:
Table 4-178 ID_ISAR5 bit assignments
Bits Name Function
[31:20] - Reserved,
RES0.
[19:16] CRC32 Indicates whether CRC32 instructions are implemented in AArch32 state:
0x1 CRC32 instructions are implemented.
[15:12] SHA2 Indicates whether SHA2 instructions are implemented in AArch32 state:
0x0 Cryptography Extensions are not implemented or are disabled.
0x1 SHA256H , SHA256H2 , SHA256SU0 , and SHA256SU1 instructions are implemented.
See the Cortex
™
-A53 MPCore Processor Cryptography Extension Technical Reference Manual for more
information.
[11:8] SHA1 Indicates whether SHA1 instructions are implemented in AArch32 state:
0x0 Cryptography Extensions are not implemented or are disabled.
0x1 SHA1C , SHA1P , SHA1M , SHA1H , SHA1SU0 , and SHA1SU1 instructions are implemented.
See the Cortex
™
-A53 MPCore Processor Cryptography Extension Technical Reference Manual for more
information.
[7:4] AES Indicates whether AES instructions are implemented in AArch32 state:
0x0 Cryptography Extensions are not implemented or are disabled.
0x2 AESE , AESD , AESMC and AESIMC , plus PMULL and PMULL2 instructions operating on 64-bit data.
See the Cortex
™
-A53 MPCore Processor Cryptography Extension Technical Reference Manual for more
information.
[3:0] SEVL Indicates whether the
SEVL instruction is implemented:
0x1 SEVL implemented to send event local.
Table 4-179 ID_ISAR5 access encoding
coproc opc1 CRn CRm opc2
1111 000 0000 0010 101
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO