System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-184
ID021414 Non-Confidential
If CSSELR indicates a cache that is not implemented, then on a read of the
CCSIDR the behavior is
CONSTRAINED UNPREDICTABLE, and can be one
of the following:
• The CCSIDR read is treated as
NOP
.
• The CCSIDR read is
UNDEFINED.
• The CCSIDR read returns an
UNKNOWN value (preferred).
Configurations CCSIDR is architecturally mapped to AArch64 register CCSIDR_EL1.
See Cache Size ID Register on page 4-43.
There is one copy of this register that is used in both Secure and
Non-secure states.
The implementation includes one CCSIDR for each cache that it can
access. CSSELR selects which Cache Size ID Register is accessible.
Attributes CCSIDR is a 32-bit register.
Figure 4-92 shows the CCSIDR bit assignments.
Figure 4-92 CCSIDR bit assignments
Table 4-180 shows the CCSIDR bit assignments.
Table 4-180 CCSIDR bit assignments
Bits Name Function
[31] WT Indicates support for Write-Through:
0
Cache level does not support Write-Through.
[30] WB Indicates support for Write-Back:
0
Cache level does not support Write-Back.
1
Cache level supports Write-Back.
[29] RA Indicates support for Read-Allocation:
0
Cache level does not support Read-Allocation.
1
Cache level supports Read-Allocation.
[28] WA Indicates support for Write-Allocation:
0
Cache level does not support Write-Allocation.
1
Cache level supports Write-Allocation.
[27:13]
NumSets
a
Indicates the number of sets in cache - 1. Therefore, a value of 0 indicates 1 set in the cache. The number
of sets does not have to be a power of 2.
[12:3]
Associativity
a
Indicates the associativity of cache - 1. Therefore, a value of 0 indicates an associativity of 1. The
associativity does not have to be a power of 2.
[2:0]
LineSize
a
Indicates the (log
2
(number of words in cache line)) - 2:
0b010
16 words per line.
a. For more information about encoding, see Table 4-181 on page 4-185.
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