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ARM Cortex-A53 MPCore - Page 253

ARM Cortex-A53 MPCore
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System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-192
ID021414 Non-Confidential
Configurations SCTLR (NS) is architecturally mapped to AArch64 register SCTLR_EL1.
See System Control Register, EL1 on page 4-50.
There are separate Secure and Non-secure copies of this register.
SCTLR has write access to the Secure copy of the register disabled when
the CP15SDISABLE signal is asserted HIGH.
Attributes SCTLR is a 32-bit register.
Figure 4-98 shows the SCTLR bit assignments.
Figure 4-98 SCTLR bit assignments
31 30 29 28 27 26 25 24 14 13 12 11 3 2 1 0
MI
RES0
VCA
EE
TRE
AFE
TE
1821 20 19
UWXN
WXN
917 16 15
RES
1
nTWE
RES
0
nTWE
RES
0
87654
CP15BEN
THEE
ITD
SED
RES
0
RES
0
23 22
RES
0
RES
1
RES
1

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