System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-191
ID021414 Non-Confidential
Configurations VMPIDR is architecturally mapped to AArch64 register
VMPIDR_EL2[31:0]. See Virtualization Multiprocessor ID Register on
page 4-50.
This register is accessible only at EL2 or EL3.
Attributes VMPIDR is a 32-bit register.
VMPIDR resets to the value of MPIDR.
Figure 4-97 shows the VMPIDR bit assignments.
Figure 4-97 VMPIDR bit assignments
Table 4-191 shows the VMPIDR bit assignments.
To access the VMPIDR:
MRC p15,4,<Rt>,c0,c0,5 ; Read VMPIDR into Rt
MCR p15,4,<Rt>,c0,c0,5 ; Write Rt to VMPIDR
Register access is encoded as follows:
4.5.27 System Control Register
The SCTLR characteristics are:
Purpose Provides the top level control of the system, including its memory system.
Usage constraints The SCTLR is accessible as follows:
Control bits in the SCTLR that are not applicable to a VMSA
implementation read as the value that most closely reflects that
implementation, and ignore writes.
Some bits in the register are read-only. These bits relate to
non-configurable features of an implementation, and are provided for
compatibility with previous versions of the architecture.
Table 4-191 VMPIDR bit assignments
Bits Name Function
[31:0] VMPIDR MPIDR value returned by Non-secure EL1 reads of the MPIDR. The MPIDR description defines the subdivision
of this value. See MPIDR bit assignments on page 4-159.
Table 4-192 VMPIDR access encoding
coproc opc1 CRn CRm opc2
1111 100 0000 0000 101
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RWRWRWRW RW
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