ARM Cortex-A53 MPCore - Page 251

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-190
ID021414 Non-Confidential
Usage constraints This register is accessible as follows:
Configurations VPIDR is architecturally mapped to AArch64 register VPIDR_EL2. See
Virtualization Processor ID Register on page 4-49.
Attributes VPIDR is a 32-bit register.
VPIDR resets to the value of MIDR.
Figure 4-96 shows the VPIDR bit assignments.
Figure 4-96 VPIDR bit assignments
Table 4-189 shows the VPIDR bit assignments.
To access the VPIDR:
MRC p15,4,<Rt>,c0,c0,0 ; Read VPIDR into Rt
MCR p15,4,<Rt>,c0,c0,0 ; Write Rt to VPIDR
Register access is encoded as follows:
4.5.26 Virtualization Multiprocessor ID Register
The VMPIDR characteristics are:
Purpose Provides the value of the Virtualization Multiprocessor ID. This is the
value returned by Non-secure EL1 reads of MPIDR.
Usage constraints This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
----RWRW -
31
0
VPIDR
Table 4-189 VPIDR bit assignments
Bits Name Function
[31:0] VPIDR MIDR value returned by Non-secure PL1 reads of the MIDR. The MIDR description defines the subdivision of
this value. See MIDR bit assignments on page 4-157.
Table 4-190 VPIDR access encoding
coproc opc1 CRn CRm opc2
1111 100 0000 0000 000
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
----RWRW -