System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-189
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Figure 4-95 CTR bit assignments
Table 4-59 on page 4-47 shows the CTR bit assignments.
To access the CTR:
MRC p15,0,<Rt>,c0,c0,1 ; Read CTR into Rt
Register access is encoded as follows:
4.5.25 Virtualization Processor ID Register
The VPIDR characteristics are:
Purpose Holds the value of the Virtualization Processor ID. This is the value
returned by Non-secure EL1 reads of MIDR.See MIDR bit assignments on
page 4-157.
Table 4-187 CTR bit assignments
Bits Name Function
[31] - Reserved,
RES1.
[30:28] - Reserved,
RES0.
[27:24] CWG Cache Write-Back granule. Log
2
of the number of words of the maximum size of memory that can be
overwritten as a result of the eviction of a cache entry that has had a memory location in it modified:
0x4
Cache Write-Back granule size is 16 words.
[23:20] ERG Exclusives Reservation Granule. Log
2
of the number of words of the maximum size of the reservation granule
that has been implemented for the Load-Exclusive and Store-Exclusive instructions:
0x4
Exclusive reservation granule size is 16 words.
[19:16] DminLine Log
2
of the number of words in the smallest cache line of all the data and unified caches that the processor
controls:
0x4
Smallest data cache line size is 16 words.
[15:14] L1lp L1 Instruction cache policy. Indicates the indexing and tagging policy for the L1 Instruction cache:
0b10
Virtually Indexed Physically Tagged (VIPT).
[13:4] - Reserved,
RES0.
[3:0] IminLine Log
2
of the number of words in the smallest cache line of all the instruction caches that the processor controls.
0x4
Smallest instruction cache line size is 16 words.
Table 4-188 CTR access encoding
coproc opc1 CRn CRm opc2
1111 010 0000 0000 001
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