System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-188
ID021414 Non-Confidential
Table 4-185 shows the CSSELR bit assignments.
To access the CSSELR:
MRC p15, 2, <Rt>, c0, c0, 0; Read CSSELR into Rt
MCR p15, 2, <Rt>, c0, c0, 0; Write Rt to CSSELR
Register access is encoded as follows:
4.5.24 Cache Type Register
The CTR_EL0 characteristics are:
Purpose Provides information about the architecture of the caches.
Usage constraints This register is accessible as follows:
Configurations CTR is architecturally mapped to AArch64 register CTR_EL0. See Cache
Type Register on page 4-47.
There is one copy of this register that is used in both Secure and
Non-secure states.
Attributes CTR is a 32-bit register.
Figure 4-95 on page 4-189 shows the CTR bit assignments.
Table 4-185 CSSELR bit assignments
Bits Name Function
[31:4] - Reserved,
RES0.
[3:1]
Level
a
a. The combination of Level=
0b001
and InD=
1
is
reserved.
Cache level of required cache:
0b000
L1.
0b001
L2.
0b010
-
0b111
Reserved.
[0]
InD
a
Instruction not Data bit:
0
Data or unified cache.
1
Instruction cache.
Table 4-186 CSSELR access encoding
coproc opc1 CRn CRm opc2
1111 010 0000 0001 000
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
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