System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-187
ID021414 Non-Confidential
MRC p15,1,<Rt>,c0,c0,1 ; Read CLIDR into Rt
Register access is encoded as follows:
4.5.22 Auxiliary ID Register
The processor does not implement AIDR, so this register is always
RES0.
4.5.23 Cache Size Selection Register
The CSSELR characteristics are:
Purpose Selects the current CCSIDR, see Cache Size ID Register on page 4-183,
by specifying:
• The required cache level.
• The cache type, either instruction or data cache.
Usage constraints This register is accessible as follows:
If the CSSELR level field is programmed to a cache level that is not
implemented, then a read of CSSELR returns an
UNKNOWN value in
CSSELR.Level.
Configurations CSSELR (NS) is architecturally mapped to AArch64 register
CSSELR_EL1. See Cache Size Selection Register on page 4-45.
There are separate Secure and Non-secure copies of this register.
Attributes CSSELR is a 32-bit register.
Figure 4-94 shows the CSSELR bit assignments.
Figure 4-94 CSSELR bit assignments
Table 4-184 CLIDR access encoding
coproc opc1 CRn CRm opc2
1111 001 0000 0000 001
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RW RW RW RW RW
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