ARM Cortex-A53 MPCore - Page 247

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-186
ID021414 Non-Confidential
Usage constraints This register is accessible as follows:
Configurations CLIDR is architecturally mapped to AArch64 register CLIDR_EL1. See
Cache Level ID Register on page 4-44.
There is one copy of this register that is used in both Secure and
Non-secure states.
Attributes CLIDR is a 32-bit register.
Figure 4-93 shows the CLIDR bit assignments.
Figure 4-93 CLIDR bit assignments
Table 4-183 shows the CLIDR bit assignments.
To access the CLIDR:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
--RORORORO RO
LoUIS
RES 0
Ctype3 Ctype2 Ctype1
31 30 29 27 26 24 23 21 20 9 8 6 5 3 2 0
LoUU LoC
RES 0
Table 4-183 CLIDR bit assignments
Bits Name Function
[31:30] - Reserved,
RES0.
[29:27] LoUU Indicates the Level of Unification Uniprocessor for the cache hierarchy:
0b0001 L1 cache is the last level of cache that must be cleaned or invalidated when cleaning or
invalidating to the point of unification for the processor.
[26:24] LoC Indicates the Level of Coherency for the cache hierarchy:
0b0001 L2 cache not implemented.
0b0010 A clean to the point of coherency operation requires the L1 and L2 caches to be cleaned.
[23:21] LoUIS Indicates the Level of Unification Inner Shareable for the cache hierarchy:
0b001 L2 cache.
L2 cache is the last level of cache that must be cleaned or invalidated when cleaning or
invalidating to the point of unification for the Inner Shareable shareability domain.
[20:6] - Reserved,
RES0.
[8:6] Ctype3
a
Indicates the type of cache if the processor implements L3 cache:
0b000 L3 cache not implemented.
[5:3] Ctype2 Indicates the type of cache if the processor implements L2 cache:
0b000 L2 cache is not implemented.
0b100 L2 cache is implemented as a unified cache.
[2:0] Ctype1 Indicates the type of cache implemented at L1:
0b011 Separate instruction and data caches at L1.
a. If software reads the Cache Type fields from Ctype1 upwards, after it has seen a value of 0b000 , no caches exist at further-out levels of the
hierarchy. So, for example, if Ctype2 is the first Cache Type field with a value of
0b000 , the value of Ctype3 must be ignored.