ARM Cortex-A53 MPCore - Page 261

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-200
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Table 4-196 shows the SCR bit assignments.
Table 4-196 SCR bit assignments
Bits Name Function
[31:14] - Reserved,
RES0.
[13] TWE Trap
WFE instructions. The possible values are:
0 WFE instructions are not trapped. This is the reset value.
1 WFE instructions executed in any mode other than Monitor mode are trapped to Monitor mode as
UNDEFINED if the instruction would otherwise cause suspension of execution, that is if:
• The event register is not set.
• There is not a pending WFE wakeup event.
• The instruction does not cause another exception.
[12] TWI Trap
WFI instructions. The possible values are:
0 WFI instructions are not trapped. This is the reset value.
1 WFI instructions executed in any mode other than Monitor mode are trapped to Monitor mode as
UNDEFINED if the instruction would otherwise cause suspension of execution.
[11:10] - Reserved,
RES0.