System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-201
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To access the SCR:
MRC p15,0,<Rt>,c1,c1,0 ; Read SCR into Rt
MCR p15,0,<Rt>,c1,c1,0 ; Write Rt to SCR
4.5.31 Secure Debug Enable Register
The SDER characteristics are:
Purpose Controls invasive and non-invasive debug in the Secure EL0 state.
[9] SIF Secure Instruction Fetch. When the processor is in Secure state, this bit disables instruction fetches from
Non-secure memory. The possible values are:
0
Secure state instruction fetches from Non-secure memory permitted. This is the reset value.
1
Secure state instruction fetches from Non-secure memory not permitted.
[8] HCE Hyp Call enable. This bit enables use of the HVC instruction from Non-secure EL1 modes. The possible values
are:
0
The
HVC
instruction is UNDEFINED in any mode. This is the reset value.
1
The
HVC
instruction enabled in Non-secure EL1, and performs a Hyp Call.
[7] SCD Secure Monitor Call disable. Makes the SMC instruction
UNDEFINED in Non-secure state. The possible values are:
0
SMC
executes normally in Non-secure state, performing a Secure Monitor Call. This is the reset
value.
1
The
SMC
instruction is UNDEFINED in Non-secure state.
A trap of the SMC instruction to Hyp mode takes priority over the value of this bit.
[6] nET Not Early Termination. This bit disables early termination.
This bit is not implemented, RES0.
[5] AW A bit writable. This bit controls whether CPSR.A can be modified in Non-secure state.
• CPSR.A can be modified only in Secure state. This is the reset value.
• CPSR.A can be modified in any security state.
[4] FW F bit writable. This bit controls whether CPSR.F can be modified in Non-secure state:
• CPSR.F can be modified only in Secure state. This is the reset value.
• CPSR.F can be modified in any security state.
[3] EA External Abort handler. This bit controls which mode takes external aborts. The possible values are:
0
External aborts taken in abort mode. This is the reset value.
1
External aborts taken in Monitor mode.
[2] FIQ FIQ handler. This bit controls which mode takes FIQ exceptions. The possible values are:
0
FIQs taken in FIQ mode. This is the reset value.
1
FIQs taken in Monitor mode.
[1] IRQ IRQ handler. This bit controls which mode takes IRQ exceptions. The possible values are:
0
IRQs taken in IRQ mode. This is the reset value.
1
IRQs taken in Monitor mode.
[0] NS Non-secure bit. Except when the processor is in Monitor mode, this bit determines the security state of the
processor. The possible values are:
0
Processor is in secure state. This is the reset value.
1
Processor is in non-secure state.
Table 4-196 SCR bit assignments (continued)
Bits Name Function
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