System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-202
ID021414 Non-Confidential
Usage constraints This register is accessible as follows:
Configurations SDER is architecturally mapped to AArch64 register SDER32_EL3. See
Secure Debug Enable Register on page 4-78.
This register is accessible only in Secure state.
Attributes SDER is a 32-bit register.
Figure 4-102 shows the SDER bit assignments.
Figure 4-102 SDER bit assignments
Table 4-197 shows the SDER bit assignments.
To access the SDER:
MRC p15,0,<Rt>,c1,c1,1 ; Read SDER into Rt
MCR p15,0,<Rt>,c1,c1,1 ; Write Rt to SDER
4.5.32 Non-Secure Access Control Register
The NSACR characteristics are:
Purpose Defines the Non-secure access permission to CP0 to CP13.
Usage constraints This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
---RW-RW RW
Table 4-197 SDER bit assignments
Bits Name Function
[31:2] - Reserved,
RES0.
[1] SUNIDEN Secure User Non-invasive Debug Enable. The possible values are:
0
Non-invasive debug not permitted in Secure EL0 state. This is the Warm reset value.
1
Non-invasive debug permitted in Secure EL0 state.
[0] SUIDEN Secure User Invasive Debug Enable. The possible values are:
0
Invasive debug not permitted in Secure EL0 state. This is the Warm reset value.
1
Invasive debug permitted in Secure EL0 state.
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RW RW
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