System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-215
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[12] DC Default cacheable. When this bit is set to 1, and the Non-secure EL1 and EL0 stage 1 MMU is disabled, the
memory type and attributes determined by the stage 1 translation is Normal, Non-shareable, Inner Write-Back
Write-Allocate, Outer Write-Back Write-Allocate.
The reset value is 0.
[11:10] BSU Barrier Shareability upgrade. The value in this field determines the minimum shareability domain that is applied
to any barrier executed from EL1 or EL0. The possible values are:
0b00
No effect.
0b01
Inner Shareable.
0b10
Outer Shareable.
0b11
Full System.
The reset value is 0.
Table 4-202 HCR bit assignments (continued)
Bits Name Function
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