System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-216
ID021414 Non-Confidential
To access the HCR:
MRC p15, 4, <Rt>, c1, c1, 0; Read Hyp Configuration Register
MCR p15, 4, <Rt>, c1, c1, 0; Write Hyp Configuration Register
4.5.37 Hyp Configuration Register 2
The HCR2 characteristics are:
Purpose Provides additional configuration controls for virtualization.
[9] FB Force broadcast. When 1, this causes the following instructions to be broadcast within the Inner Shareable domain
when executed from Non-secure EL1:
TLBIALL
,
TLBIMVA
,
TLBIASID
,
TLBIMVAA
,
BPIALL
, and
ICIALLU
.
The reset value is 0.
[8] VA Virtual Asynchronous Abort exception. When the AMO bit is set to 1, setting this bit signals a virtual
Asynchronous Abort exception to the Guest OS, when the processor is executing in Non-secure state at EL0 or
EL1.
The Guest OS cannot distinguish the virtual exception from the corresponding physical exception.
The reset value is 0.
[7] VI Virtual IRQ exception. When the IMO bit is set to 1, setting this bit signals a virtual IRQ exception to the Guest
OS, when the processor is executing in Non-secure state at EL0 or EL1.
The Guest OS cannot distinguish the virtual exception from the corresponding physical exception.
The reset value is 0.
[6] VF Virtual FIQ exception. When the FMO bit is set to 1, setting this bit signals a virtual FIQ exception to the Guest
OS, when the processor is executing in Non-secure state at EL0 or EL1.
The Guest OS cannot distinguish the virtual exception from the corresponding physical exception.
The reset value is 0.
[5] AMO Asynchronous Abort Mask Override. When this is set to 1, it overrides the effect of CPSR.A, and enables virtual
exception signalling by the VA bit.
The reset value is 0.
[4] IMO IRQ Mask Override. When this is set to 1, it overrides the effect of CPSR.I, and enables virtual exception
signalling by the VI bit.
The reset value is 0.
[3] FMO FIQ Mask Override. When this is set to 1, it overrides the effect of CPSR.F, and enables virtual exception
signalling by the VF bit.
The reset value is 0.
[2] PTW Protected Table Walk. When 1, if the stage 2 translation of a translation table access made as part of a stage 1
translation table walk at EL0 or EL1 maps that translation table access to Device memory, the access is faulted
as a stage 2 Permission fault.
The reset value is 0.
[1] SWIO Set/Way Invalidation Override. When 1, this causes EL1 execution of the data cache invalidate by set/way
instruction to be treated as data cache clean and invalidate by set/way.
DCISW
is executed as
DCCISW
.
This bit is
RES1.
[0] VM Second stage of Translation enable. When 1, this enables the second stage of translation for execution in EL1 and
EL0.
The reset value is 0.
Table 4-202 HCR bit assignments (continued)
Bits Name Function
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