System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-220
ID021414 Non-Confidential
Table 4-204 HDCR bit assignments
Bits Name Function
[31:12] - Reserved,
RES0.
[11] TDRA Trap debug ROM address register access.
0
Has no effect on accesses to debug ROM address registers from EL1 and EL0.
1
Trap valid Non-secure EL1 and EL0 access to debug ROM address registers to Hyp mode.
When this bit is set to 1, any valid Non-secure access to the following registers is trapped to Hyp mode:
• DBGDRAR.
•DBGDSAR.
If HCR.TGE is 1 or HDCR.TDE is 1, then this bit is ignored and treated as though it is 1 other than for the value
read back from HDCR.
On Warm reset, the field resets to 0.
[10] TDOSA Trap Debug OS-related register access:
0
Has no effect on accesses to CP14 Debug registers.
1
Trap valid Non-secure accesses to CP14 OS-related Debug registers to Hyp mode.
When this bit is set to 1, any valid Non-secure CP14 access to the following OS-related Debug registers is
trapped to Hyp mode:
• DBGOSLSR.
•DBGOSLAR.
•DBGOSDLR.
• DBGPRCR.
If HCR.TGE is 1 or HDCR.TDE is 1, then this bit is ignored and treated as though it is 1 other than for the value
read back from HDCR.
On Warm reset, the field resets to 0.
[9] TDA Trap Debug Access:
0
Has no effect on accesses to CP14 Debug registers.
1
Trap valid Non-secure accesses to CP14 Debug registers to Hyp mode.
When this bit is set to 1, any valid access to the CP14 Debug registers, other than the registers trapped by the
TDRA and TDOSA bits, is trapped to Hyp mode.
If HCR.TGE is 1 or HDCR.TDE is1, then this bit is ignored and treated as though it is 1 other than for the value
read back from HDCR.
On Warm reset, the field resets to 0.
[8] TDE Trap Debug Exceptions:
0
Has no effect on Debug exceptions.
1
Route Non-secure Debug exceptions to Hyp mode.
When this bit is set to 1, any Debug exception taken in Non-secure state is trapped to Hyp mode.
If HCR.TGE is 1, then this bit is ignored and treated as though it is 1 other than for the value read back from
HDCR.This bit resets to 0.
[7] HPME Hypervisor Performance Monitor Enable:
0
Hyp mode performance monitor counters disabled.
1
Hyp mode performance monitor counters enabled.
When this bit is set to 1, access to the performance monitors that are reserved for use from Hyp mode is enabled.
For more information, see the description of the HPMN field.
The reset value of this bit is
UNKNOWN.
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