System Control
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To access the HDCR:
MRC p15,4,<Rt>,c1,c1,1 ; Read HDCR into Rt
MCR p15,4,<Rt>,c1,c1,1 ; Write Rt to HDCR
4.5.39 Hyp Architectural Feature Trap Register
The HCPTR characteristics are:
Purpose Controls trapping to Hyp mode of Non-secure access, at EL1 or lower, to
coprocessors other than CP14 and CP15 and to floating-point and
Advanced SIMD functionality. Also controls access from Hyp mode to
this functionality.
[6] TPM Trap Performance Monitor accesses:
0
Has no effect on performance monitor accesses.
1
Trap valid Non-secure performance monitor accesses to Hyp mode.
When this bit is set to 1, any valid Non-secure access to the Performance Monitor registers is trapped to Hyp
mode. This bit resets to 0. See the ARM
®
Architecture Reference Manual ARMv8, for ARMv8-A architecture
profile for more information.
[5] TPMCR Trap Performance Monitor Control Register accesses:
0
Has no effect on PMCR accesses.
1
Trap valid Non-secure PMCR accesses to Hyp mode.
When this bit is set to 1, any valid Non-secure access to the PMCR is trapped to Hyp mode. This bit resets to 0.
See the ARM
®
Architecture Reference Manual ARMv8, for ARMv8-A architecture profile for more information.
[4:0] HPMN Hyp Performance Monitor count. Defines the number of Performance Monitors counters that are accessible
from Non-secure EL1 and EL0 modes if unprivileged access is enabled.
In Non-secure state, HPMN divides the Performance Monitors counters as follows. If software is accessing
Performance Monitors counter n then, in Non-secure state:
For example, If PMnEVCNTR is performance monitor counter n then, in Non-secure state:
• If n is in the range 0 ≤ n < HPMN, the counter is accessible from EL1 and EL2, and from EL0 if
unprivileged access to the counters is enabled.
• If n is in the range HPMN ≤ n <PMCR.N, the counter is accessible only from EL2. The HPME bit enables
access to the counters in this range.
If this field is set to 0, or to a value larger than PMCR.N, then the behavior in Non-secure EL0 and EL1 is
CONSTRAINED UNPREDICTABLE, and one of the following must happen:
• The number of counters accessible is an UNKNOWN non-zero value less than PMCR.N.
• There is no access to any counters.
For reads of HDCR.HPMN by EL2 or higher, if this field is set to 0 or to a value larger than PMCR.N, the
processor must return a
CONSTRAINED UNPREDICTABLE value being one of:
•PMCR.N.
• The value that was written to HDCR.HPMN.
• (The value that was written to HDCR.HPMN) modulo 2h, where h is the smallest number of bits required
for a value in the range 0 to PMCR.N.
This field resets to
0x6
.
Table 4-204 HDCR bit assignments (continued)
Bits Name Function
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