System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-224
ID021414 Non-Confidential
MRC p15,4,<Rt>,c1,c1,2 ; Read HCPTR into Rt
MCR p15,4,<Rt>,c1,c1,2 ; Write Rt to HCPTR
4.5.40 Translation Table Base Register 0
The TTBR0 characteristics are:
Purpose Holds the base address of translation table 0, and information about the
memory it occupies. This is one of the translation tables for the stage 1
translation of memory accesses from modes other than Hyp mode.
Usage constraints This register is accessible as follows:
Used in conjunction with the TTBCR. When the 64-bit TTBR0 format is
used, cacheability and shareability information is held in the TTBCR and
not in TTBR0.
Configurations TTBR0 (NS) is architecturally mapped to AArch64 register TTBR0_EL1.
See Translation Table Base Register 0, EL1 on page 4-79.
TTBR0 (S) is mapped to AArch64 register TTBR0_EL3. See Translation
Table Base Register 0, EL3 on page 4-93.
There are separate Secure and Non-secure copies of this register.
TTBR0 has write access to the Secure copy of the register disabled when
the CP15SDISABLE signal is asserted HIGH.
Attributes TTBR0 is:
• A 32-bit register when TTBCR.EAE is 0.
• A 64-bit register when TTBCR.EAE is 1.
There are different formats for this register. TTBCR.EAE determines which format of the
register is used. This section describes:
• TTBR0 format when using the Short-descriptor translation table format.
• TTBR0 format when using the Long-descriptor translation table format on page 4-225.
TTBR0 format when using the Short-descriptor translation table format
Figure 4-111 shows the TTBR0 bit assignments when TTBCR.EAE is 0.
Figure 4-111 TTBR0 bit assignments, TTBCR.EAE is 0
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RWRWRWRW RW
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