System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-236
ID021414 Non-Confidential
4.5.46 Hyp System Trap Register
The HSTR characteristics are:
Purpose Controls trapping to Hyp mode of Non-secure accesses, at EL1 or lower,
of use of T32EE, or the CP15 primary registers, {c0-c3,c5-c13,c15}.
Usage constraints This register is accessible as follows:
Configurations HSTR is architecturally mapped to AArch64 register HSTR_EL2.
This register is accessible only at EL2 or EL3.
Attributes HSTR is a 32-bit register.
Figure 4-120 shows the HSTR bit assignments.
Figure 4-120 HSTR bit assignments
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
----RWRW -
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