ARM Cortex-A53 MPCore - Page 298

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-237
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Table 4-215 shows the HSTR bit assignments.
Table 4-215 HSTR bit assignments
Bits Name Function
[31:17] - Reserved,
RES0.
[16] TTEE Trap T32EE. This value is:
0 T32EE is not supported.
[15] T15 Trap coprocessor primary register CRn = 15. The possible values are:
0 Has no effect on Non-secure accesses to CP15 registers.
1 Trap valid Non-secure accesses to coprocessor primary register CRn = 15 to Hyp mode.
The reset value is 0.
[14] - Reserved,
RES0.
[13] T13 Trap coprocessor primary register CRn = 13. The possible values are:
0 Has no effect on Non-secure accesses to CP15 registers.
1 Trap valid Non-secure accesses to coprocessor primary register CRn = 13 to Hyp mode.
The reset value is 0.
[12] T12 Trap coprocessor primary register CRn = 12. The possible values are:
0 Has no effect on Non-secure accesses to CP15 registers.
1 Trap valid Non-secure accesses to coprocessor primary register CRn = 12 to Hyp mode.
The reset value is 0.
[11] T11 Trap coprocessor primary register CRn = 11. The possible values are:
0 Has no effect on Non-secure accesses to CP15 registers.
1 Trap valid Non-secure accesses to coprocessor primary register CRn = 11 to Hyp mode.
The reset value is 0.
[10] T10 Trap coprocessor primary register CRn = 10. The possible values are:
0 Has no effect on Non-secure accesses to CP15 registers.
1 Trap valid Non-secure accesses to coprocessor primary register CRn = 10 to Hyp mode.
The reset value is 0.