System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-243
ID021414 Non-Confidential
Table 4-218 shows how the LL bits in the Status field encode the lookup level associated with
the MMU fault.
To access the DFSR:
MRC p15, 0, <Rt>, c5, c0, 0; Read DFSR into Rt
MCR p15, 0, <Rt>, c5, c0, 0; Write Rt to DFSR
4.5.49 Instruction Fault Status Register
The IFSR characteristics are:
Purpose Holds status information about the last instruction fault.
Usage constraints This register is accessible as follows:
Configurations IFSR (NS) is architecturally mapped to AArch64 register IFSR32_EL2.
See Instruction Fault Status Register, EL2 on page 4-98.
There are separate Secure and Non-secure copies of this register.
Attributes IFSR is a 32-bit register.
There are two formats for this register. The current translation table format determines which
format of the register is used. This section describes:
• IFSR when using the Short-descriptor translation table format.
• IFSR when using the Long-descriptor translation table format on page 4-244.
IFSR when using the Short-descriptor translation table format
Figure 4-123 shows the IFSR bit assignments when using the Short-descriptor translation table
format.
Figure 4-123 IFSR bit assignments for Short-descriptor translation table format
Table 4-218 Encodings of LL bits associated with the MMU fault
Bits Meaning
0b00
Reserved
0b01
Level 1
0b10
Level 2
0b11
Level 3
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RW RW RW RW RW
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