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ARM Cortex-A53 MPCore - Page 305

ARM Cortex-A53 MPCore
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System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-244
ID021414 Non-Confidential
Table 4-219 shows the IFSR bit assignments when using the Short-descriptor translation table
format.
IFSR when using the Long-descriptor translation table format
Figure 4-124 shows the IFSR bit assignments when using the Long-descriptor translation table
format.
Figure 4-124 IFSR bit assignments for Long-descriptor translation table format
Table 4-219 IFSR bit assignments for Short-descriptor translation table format
Bits Name Function
[31:13] - Reserved, RES0.
[12] ExT External abort type. This field indicates whether an AXI Decode or Slave error caused an abort:
0
External abort marked as DECERR.
1
External abort marked as SLVERR.
For aborts other than external aborts this bit always returns 0.
[11] - Reserved,
RES0.
[10] FS[4] Part of the Fault Status field. See bits [3:0] in this table.
[9] - RAZ.
[8:5] - Reserved,
RES0.
[4:0] FS[3:0] Fault Status bits. This field indicates the type of exception generated. Any encoding not listed is reserved.
0b00010
Debug event.
0b00011
Access flag fault, section.
0b00101
Translation fault, section.
0b00110
Access flag fault, page.
0b00111
Translation fault, page.
0b01000
Synchronous external abort, non-translation.
0b01001
Domain fault, section.
0b01011
Domain fault, page.
0b01100
Synchronous external abort on translation table walk, first level.
0b01101
Permission Fault, Section.
0b01110
Synchronous external abort on translation table walk, second Level.
0b01111
Permission fault, page.
0b10000
TLB conflict abort.
0b11001
Synchronous parity error on memory access.
0b11100
Synchronous parity error on translation table walk, first level.
0b11110
Synchronous parity error on translation table walk, second level.
31 13 12 11 10 9 8 5 0
RES01
ExT
RES0 Status
6
RES0

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