System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-245
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Table 4-220 shows the IFSR bit assignments when using the Long-descriptor translation table
format.
Table 4-221 shows how the LL bits in the Status field encode the lookup level associated with
the MMU fault.
If a Data Abort exception is generated by an instruction cache maintenance operation when the
Long-descriptor translation table format is selected, the fault is reported as a Cache Maintenance
fault in the DFSR or HSR with the appropriate Fault Status code. For such exceptions reported
in the DFSR, the corresponding IFSR is
UNKNOWN.
To access the IFSR:
MRC p15, 0, <Rt>, c5, c0, 1; Read IFSR into Rt
MCR p15, 0, <Rt>, c5, c0, 1; Write Rt to IFSR
Table 4-220 IFSR bit assignments for Long-descriptor translation table format
Bits Name Function
[31:13] - Reserved,
RES0.
[12] ExT External abort type. This field indicates whether an AXI Decode or Slave error caused an abort:
0
External abort marked as DECERR.
1
External abort marked as SLVERR.
For aborts other than external aborts this bit always returns 0.
[11:10] - Reserved,
RES0.
[9] - RAO.
[8:6] - Reserved, RES0.
[5:0] Status Fault Status bits. This field indicates the type of exception generated. Any encoding not listed is reserved.
0b000000
Address size fault in TTBR0 or TTBR1.
0b0001LL
Translation fault, LL bits indicate level.
0b0010LL
Access fault flag, LL bits indicate level.
0b0011LL
Permission fault, LL bits indicate level.
0b010000
Synchronous external abort.
0b0101LL
Synchronous external abort on translation table walk, LL bits indicate level.
0b011000
Synchronous parity error on memory access.
0b0111LL
Synchronous parity error on memory access on translation table walk, LL bits indicate level.
0b100001
Alignment fault.
0b100010
Debug event.
0b110000
TLB conflict abort.
Table 4-221 Encodings of LL bits associated with the MMU fault
Bits Meaning
0b00
Reserved
0b01
Level 1
0b10
Level 2
0b11
Level 3
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