System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-246
ID021414 Non-Confidential
Register access is encoded as follows:
4.5.50 Auxiliary Data Fault Status Register
The processor does not implement ADFSR, so this register is always
RES0.
4.5.51 Auxiliary Instruction Fault Status Register
The processor does not implement AIFSR, so this register is always
RES0.
4.5.52 Hyp Auxiliary Data Fault Status Syndrome Register
The processor does not implement HADFSR, so this register is always
RES0.
4.5.53 Hyp Auxiliary Instruction Fault Status Syndrome Register
The processor does not implement HAIFSR, so this register is always
RES0.
4.5.54 Hyp Syndrome Register
The HSR characteristics are:
Purpose Holds syndrome information for an exception taken to Hyp mode.
Usage constraints This register is accessible as follows:
Configurations HSR is architecturally mapped to AArch64 register ESR_EL2. See
Exception Syndrome Register, EL2 on page 4-101.
This register is accessible only at EL2 or EL3.
Attributes HSR is a 32-bit register.
Figure 4-125 shows the HSR bit assignments.
Figure 4-125 HSR bit assignments
Table 4-222 IFSR access encoding
coproc opc1 CRn CRm opc2
1111 000 0101 0000 001
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
----RWRW -
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