ARM Cortex-A53 MPCore - Page 311

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-250
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4.5.58 Hyp Instruction Fault Address Register
The HIFAR characteristics are:
Purpose Holds the virtual address of the faulting address that caused a synchronous
Prefetch Abort exception that is taken to Hyp mode.
Usage constraints This register is accessible as follows:
Execution in any Non-secure mode other than Hyp mode makes HPFAR
UNKNOWN.
Configurations HIFAR is architecturally mapped to AArch64 register FAR_EL2[63:32].
See Fault Address Register, EL2 on page 4-104.
HIFAR is architecturally mapped to AArch32 register IFAR (S). See
Instruction Fault Address Register on page 4-248.
Attributes HIFAR is a 32-bit register.
Figure 4-129 shows the HIFAR bit assignments.
Figure 4-129 HIFAR bit assignments
Table 4-227 shows the HIFAR bit assignments.
To access the HIFAR:
MRC p15, 4, <Rt>, c6, c0, 2 ; Read HIFAR into Rt
MCR p15, 4, <Rt>, c6, c0, 2 ; Write Rt to HIFAR
4.5.59 Hyp IPA Fault Address Register
The HPFAR characteristics are:
Purpose Holds the faulting IPA for some aborts on a stage 2 translation taken to
Hyp mode.
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
----RWRW -
31
0
VA of faulting address of synchronous Prefetch Abort exception
Table 4-227 HIFAR bit assignments
Bits Name Function
[31:0] VA The Virtual Address of faulting address of synchronous Prefetch Abort exception