ARM Cortex-A53 MPCore - Page 312

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-251
ID021414 Non-Confidential
Usage constraints This register is accessible as follows:
Execution in any Non-secure mode other than Hyp mode makes HPFAR
UNKNOWN.
Configurations HPFAR is architecturally mapped to AArch64 register
HPFAR_EL2[31:0]. See Hypervisor IPA Fault Address Register, EL2 on
page 4-105.
Attributes HPFAR is a 32-bit register.
Figure 4-129 on page 4-250 shows the HPFAR bit assignments.
Figure 4-130 HPFAR bit assignments
on page 4-104Table 4-227 on page 4-250 shows the HPFAR bit assignments.
To access the HPFAR:
MRC p15, 4, <Rt>, c6, c0, 4 ; Read HPFAR into Rt
MCR p15, 4, <Rt>, c6, c0, 4 ; Write Rt to HPFAR
4.5.60 Physical Address Register
The processor does not use any implementation-defined bits in the 32-bit format or 64-bit
format PAR. Bit[8] is
RES0. See the ARM
®
Architecture Reference Manual ARMv8, for
ARMv8-A architecture profile for more information.
4.5.61 L2 Control Register
The L2CTLR characteristics are:
Purpose Provides
IMPLEMENTATION DEFINED control options for the L2 memory
system.
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
----RWRW -
31
0
FIPA[39:12]
43
RES0
Table 4-228 HPFAR bit assignments
Bits Name Function
[31:4] FIPA[39:12] Bits [39:12] of the faulting intermediate physical address
[3:0] - Reserved, RES0