System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-252
ID021414 Non-Confidential
Usage constraints This register is accessible as follows:
L2CTLR is writeable. However, all writes to this register are ignored.
Configurations L2CTLR is architecturally mapped to the AArch64 L2CTLR_EL1
register. See L2 Control Register on page 4-106.
There is one L2CTLR for the Cortex-A53 processor.
There is one copy of this register that is used in both Secure and
Non-secure states.
Attributes L2CTLR is a 32-bit register.
Figure 4-131 shows the L2CTLR bit assignments.
Figure 4-131 L2CTLR bit assignments
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RW RW RW RW RW
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