System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-253
ID021414 Non-Confidential
Table 4-229 shows the L2CTLR bit assignments.
To access the L2CTLR:
MRC p15, 1, <Rt>, c9, c0, 2; Read L2CTLR into Rt
4.5.62 L2 Extended Control Register
The L2ECTLR characteristics are:
Purpose Provides additional
IMPLEMENTATION DEFINED control options for the L2
memory system. This register is used for dynamically changing, but
implementation specific, control bits.
Table 4-229 L2CTLR bit assignments
Bits Name Function
[31:26] - Reserved,
RES0.
[25:24] Number of cores Number of cores present:
0b00
One core, core 0.
0b01
Two cores, core 0 and core 1.
0b10
Three cores, cores 0 to 2.
0b11
Four cores, cores 0 to 3.
These bits are read-only and the value of this field is set to the number of cores present in the
configuration.
[23] - Reserved, RAZ
[22] CPU Cache Protection CPU Cache Protection. Core RAMs are implemented:
0
without ECC.
1
with ECC.
[21] SCU-L2 Cache
Protection
SCU-L2 Cache Protection. L2 cache is implemented:
0
without ECC.
1
with ECC.
This field is RO.
[20:6] - Reserved, RAZ.
[5] Data RAM input
latency
L2 data RAM input latency
0
1-cycle input delay from L2 data RAMs.
1
2-cycle input delay from L2 data RAMs.
This field is RO.
[4:1] - Reserved, RAZ.
[0] Data RAM output
latency
L2 data RAM output latency:
0
2-cycle output delay from L2 data RAMs.
1
3-cycle output delay from L2 data RAMs.
This field is RO.
To Next Page
Loading...
