System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-256
ID021414 Non-Confidential
4.5.63 Primary Region Remap Register
The PRRR characteristics are:
Purpose Controls the top level mapping of the TEX[0], C, and B memory region
attributes.
Usage constraints This register is accessible as follows:
PRRR is not accessible when the Long-descriptor translation table format
is in use. See, instead, Memory Attribute Indirection Registers 0 and 1 on
page 4-259.
Configurations PRRR (NS) is architecturally mapped to AArch64 register
MAIR_EL1[31:0] when TTBCR.EAE is 0.
PRRR (S) is mapped to AArch64 register MAIR_EL3[31:0] when
TTBCR.EAE is 0.
There are separate Secure and Non-secure copies of this register.
PRRR has write access to the Secure copy of the register disabled when
the CP15SDISABLE signal is asserted HIGH.
Attributes PRRR is a 32-bit register when TTBCR.EAE==0.
Figure 4-133 shows the PRRR bit assignments.
Figure 4-133 PRRR bit assignments
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RW RW RW RW RW
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