ARM Cortex-A53 MPCore - Page 321

System Control
ARM DDI 0500D Copyright © 2013-2014 ARM. All rights reserved. 4-260
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Table 4-233 shows the MAIR0 and MAIR1 bit assignments.
Table 4-234 shows the Attr<n>[7:4] bit assignments.
Table 4-235 shows the Attr<n>[3:0] bit assignments. The encoding of Attr<n>[3:0] depends on
the value of Attr<n>[7:4], as Table 4-235 shows.
Table 4-233 MAIR0 and MAIR1 bit assignments
Bits Name Description
[7:0]
Attrm
a
The memory attribute encoding for an AttrIndx[2:0] entry in a Long descriptor format translation table entry, where:
• AttrIndx[2] selects the appropriate MAIR:
— setting AttrIndx[2] to 0 selects MAIR0.
— setting AttrIndx[2] to 1 selects MAIR1.
• AttrIndx[2:0] gives the value of <n> in Attr<n>.
a. Where m is 0-7.
Table 4-234 Attr<n>[7:4] bit assignments
Bits Meaning
0b0000 Device memory. See Table 4-235 for the type of Device memory.
0b00RW , RW not 00
Normal Memory, Outer Write-through transient.
a
a. The transient hint is ignored.
0b0100 Normal Memory, Outer Non-Cacheable.
0b01RW , RW not 00
Normal Memory, Outer Write-back transient.
a
0b10RW Normal Memory, Outer Write-through non-transient.
0b11RW Normal Memory, Outer Write-back non-transient.
Table 4-235 Attr<n>[3:0] bit assignments
Bits Meaning when Attr<n>[7:4] is 0000 Meaning when Attr<n>[7:4] is not 0000
0b0000 Device-nGnRnE memory UNPREDICTABLE
0b00RW , RW not 00 UNPREDICTABLE Normal Memory, Inner Write-through transient
0b0100 Device-nGnRE memory Normal memory, Inner Non-Cacheable
0b01RW , RW not 00 UNPREDICTABLE Normal Memory, Inner Write-back transient
0b1000 Device-nGRE memory Normal Memory, Inner Write-through
non-transient (RW=00)
0b10RW , RW not 00 UNPREDICTABLE Normal Memory, Inner Write-through non-transient
0b1100 Device-GRE memory Normal Memory, Inner Write-back non-transient (RW=00)
0b11RW , RW not 00 UNPREDICTABLE Normal Memory, Inner Write-back non-transient